As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, lower power consumption and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (Fin FET). In a Fin FET device, it is possible to utilize additional sidewalls and to suppress a short channel effect.
Another candidate is a gate-all-around (GAA) device. While a Fin FET device has a fin bottom portion which is not controlled by a gate, in a GAA device, all of the surfaces of the channel layer can be subject to gate control. A GAA device, such as a GAA MOSFET (or MISFET) device, includes a very narrow cylindrical channel body. In particular, a vertical GAA device (VGAA) having a channel extending in a vertical direction (i.e., perpendicular to the substrate) is a promising device as a candidate for low power SRAM applications. In the present disclosure, new layout structures and configurations of an SRAM using a VGAA device with a small unit cell area are provided.